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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999 mos integrated circuit m m m m pd45125421, 45125821, 45125161 128m-bit virtualchannel tm sdram preliminary data sheet the mark ? ? ? ? shows major revised points. document no. m14412ej3v0ds00 (3rd edition) date published november 1999 ns cp(k) printed in japan description the 128m-bit virtualchannel (vc) sdram is implemented to be 100% pin and package compatible to the industry standard sdram. it uses the same command protocol and interface as sdram. the virtualchannel sdram command set is a superset of the sdram. it also follows the same electrical and timing specifications of the sdram, such that it is possible for one product platform to be used with the virtualchannel sdram and non- virtualchannel sdram part. features fully standard synchronous dynamic ram, with all signals referenced to a positive clock edge dual internal banks controlled by bank select address sixteen channels controlled by channel select address quad segments controlled by segment select address byte control (x16) by ldqm and udqm programmable wrap sequence (sequential / interleave) programmable burst length (1, 2, 4, 8 and 16) read latency (1, 2) prefetch read latency (2, 4) : for x4 bits organization( m pd45125421), prefetch read operation can not be used. auto precharge and without auto precharge auto refresh and self refresh x4, x8, x16 organization single 3.3 v 0.3 v power supply interface: lvttl refresh cycle: 4 k cycles / 64 ms h
preliminary data sheet m14412ej3v0ds00 2 m m m m pd45125421, 45125821, 45125161 ordering information (under development) part number organization clock read prefetch channel package (word x bit x bank) frequency latency read and mhz (max.) latency interface m pd45125421g5-a75-9jf 16m x 4 x 2 133 2 - note1 16 channels 54-pin plastic 67 1 note2 - note1 and tsop(ii) m pd45125421g5-a10-9jf 100 2 - note1 lvttl (10.16mm (400)) 50 1 note2 - note1 m pd45125821g5-a75-9jf 8m x 8 x 2 133 2 4 67 1 note2 2 m pd45125821g5-a10-9jf 100 2 4 50 1 note2 2 m pd45125161g5-a75-9jf 4m x 16 x 2 133 2 4 67 1 note2 2 m pd45125161g5-a10-9jf 100 2 4 50 1 note2 2 notes 1. for x4 bits organization, prefetch read operation can not be used. 2. under development. h
preliminary data sheet m14412ej3v0ds00 3 m m m m pd45125421, 45125821, 45125161 part number m pd4 5 125 8 2 1 g5 - a75 [ x4, x8 ] interface 1 : lvttl 2 : sstl number of banks and channel 1 : 2 banks and 8 channels 2 : 2 banks and 16 channels 3 : 2 banks and 32 channels 4 : 4 banks and 8 channels 5 : 4 banks and 16 channels 6 : 4 banks and 32 channels organization 4 : x4 8 : x8 synchronous dram nec memory package g5 : tsop(ii) low voltage a : 3.3 0.3 v minimum cycle time 75 : rl=2 : 7.5 ns (133mhz) rl=1 : 15 ns ( 67mhz) 10 : rl=2 : 10 ns (100mhz) rl=1 : 20 ns ( 50mhz) data rate memory density 64m bits standard sdram 64m bits vc sdram 128m bits standard sdram 128m bits vc sdram : : : : 64 65 128 125 note note note note note note note reserved note no letter : single data rate d : double data rate h
preliminary data sheet m14412ej3v0ds00 4 m m m m pd45125421, 45125821, 45125161 m pd4 5 125 16 1 g5 - a75 [ x16 ] number of banks and interface 1 : 2 banks and lvttl 2 : 2 banks and sstl word and number of channel memory density synchronous dram nec memory package g5 : tsop(ii) low voltage a : 3.3 0.3 v data rate 64m bits standard sdram 64m bits vc sdram 128m bits standard sdram 128m bits vc sdram : : : : 64 65 128 125 note note note note reserved 15 : x16 bits and 8 channels 16 : x16 bits and 16 channels 17 : x16 bits and 32 channels note no letter : single data rate d : double data rate minimum cycle time 75 : rl=2 : 7.5 ns (133mhz) rl=1 : 15 ns ( 67mhz) 10 : rl=2 : 10 ns (100mhz) rl=1 : 20 ns ( 50mhz) h
preliminary data sheet m14412ej3v0ds00 5 m m m m pd45125421, 45125821, 45125161 pin configurations /xxx indicates active low signal. [ m m m m pd45125421] 54-pin plastic tsop (ii) (10.16mm (400)) 16m words x 4 bits x 2 banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc nc v cc q nc dq0 v ss q nc nc v cc q nc dq1 v ss q nc v cc nc /we /cas /ras /cs bank address(a13) a12 auto precharge(a10) a0 a1 a2 a3 v cc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss nc v ss q nc dq3 v cc q nc nc v ss q nc dq2 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a13 a0 - a12 a0 - a7, a10 dq0 - dq3 /cs /ras /cas /we : : : : : : : : address inputs row address inputs column address inputs data inputs/outputs chip select row address strobe column address strobe write enable dqm cke clk v cc v ss v cc q v ss q nc : : : : : : : : dq mask enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection remark refer to 1. input/ output pin function for bank address, channel address and segment address.
preliminary data sheet m14412ej3v0ds00 6 m m m m pd45125421, 45125821, 45125161 [ m m m m pd45125821] 54-pin plastic tsop (ii) (10.16mm (400)) 8m words x 8 bits x 2 banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc dq0 v cc q nc dq1 v ss q nc dq2 v cc q nc dq3 v ss q nc v cc nc /we /cas /ras /cs bank address(a13) a12 auto precharge(a10) a0 a1 a2 a3 v cc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq7 v ss q nc dq6 v cc q nc dq5 v ss q nc dq4 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a13 a0 - a12 a0 - a7 dq0 - dq7 /cs /ras /cas /we : : : : : : : : address inputs row address inputs column address inputs data inputs/outputs chip select row address strobe column address strobe write enable dqm cke clk v cc v ss v cc q v ss q nc : : : : : : : : dq mask enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection remark refer to 1. input/ output pin function for bank address, channel address and segment address.
preliminary data sheet m14412ej3v0ds00 7 m m m m pd45125421, 45125821, 45125161 [ m m m m pd45125161] 54-pin plastic tsop (ii) (10.16mm (400)) 4m words x 1 6 bits x 2 banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 v ss q dq7 v cc ldqm /we /cas /ras /cs bank address(a13) a12 auto precharge(a10) a0 a1 a2 a3 v cc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 v ss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a13 a0 - a12 a0 - a6 dq0 - dq15 /cs /ras /cas /we : : : : : : : : address inputs row address inputs column address inputs data inputs/outputs chip select row address strobe column address strobe write enable udqm ldqm cke clk v cc v ss v cc q v ss q nc : : : : : : : : : upper dq mask enable lower dq mask enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection remark refer to 1. input/ output pin function for bank address, channel address and segment address.
preliminary data sheet m14412ej3v0ds00 8 m m m m pd45125421, 45125821, 45125161 vcmemory tm architecture the vcmemory is a memory core technology designed to improve memory data throughput efficiency and initial latency of memories. intended for use in next generation memory systems, the vcmemory technology is ideal memory for a wide range of application such as multimedia pc, game machine, internet server etc. the slow core operation memory such as dram, flash memory and mask rom can get very significant performance improvements with vcmemory technology. today's memory subsystems are accessed by multiple tasks/sources (memory masters), working in multitasking mode. each memory master accesses memory with an address locality with a time locality, a block size and a number of contiguous accesses. vcmemory architecture is designed for this multitasking, multiple masters, interleaving access scenarios. the vcmemory provides memory masters with virtualchannels. each channel is a set of resources that constitute a fast dedicated path for each memory masters to access the memory. the virtualchannels will minimize the overhead resulting from other memory master's accesses, reduce the access latency and facilitate automatic data sharing. each channel is equipped with a data row buffer and its own independent operating modes. to the memory masters, this looks like its own very fast memory. the system memory controller associates these channels to the memory masters for their accesses. thus, the channels are made to track the accesses of these memory masters. the system memory controller has complete controls over the operations of the channels. it can schedule and issue commands that causes segments of memory rows to be loaded into the channels or for data from the channels to be written back to the memory rows. any channels can store the data from any rows, can be written to any rows and hence are fully associative. then the read and write operations will be occurring as much as possible with these high speed channels, minimizing all overheads associated with the dram bank operations. the read/write operations of the channels (foreground operations) can operate independently with the dram bank operations (background operations) of activate, precharge, prefetch (loading row data to channel) and restore (writing channel data to row). then vcmemory also further enhances performance by allowing the system memory controller to schedule the foreground and background operations to operate concurrently. virtualchannel sdram architecture offers the following features and benefits: 1. multiplies the effective data throughput performance of conventional dram core. 2. achieving close to full data bus bandwidth with low latency, interleaved random row, random column read/write through the channels. 3. transparent dram bank operations through the concurrent foreground and background operations 4. very wide (256 bytes wide) internal data transfer bus between channel and memory core 5. equivalence of tens of multiple memory banks by using only a fraction of the frequency of row activate and precharge of conventional dram core.
preliminary data sheet m14412ej3v0ds00 9 m m m m pd45125421, 45125821, 45125161 block diagram channel bank b sense amp. memory cell array row decoder segment decoder dqm mode register control logic command decoder clock generator cke clk bank a column decoder latch circuit data control circuit input and output buffer dq dq address buffer and refresh counter address address channel control channel selector /we /cas /ras /cs
preliminary data sheet m14412ej3v0ds00 10 m m m m pd45125421, 45125821, 45125161 conceptual schematic 1 foreground read operation write operation row decoder bank b row decoder bank a one segment : 1/4 row one segment means one data transfer size at the background operations. background prefetch operation restore operation prefetch operation (from segment of memory core to channel) restore operation (from channel to segment of memory core) write operation ( to channel ) read operation ( from channel ) 16 channels input and output buffer dq dq segment segment segment segment segment segment segment segment
preliminary data sheet m14412ej3v0ds00 11 m m m m pd45125421, 45125821, 45125161 conceptual schematic 2 prefetch operation the data is fetched from a segment to any channel buffer. segment segment segment segment segment segment segment segment 16 channels row decoder bank b row decoder bank a restore operation the data is transferred from a channel buffer to any segment. 16 channels row decoder bank b row decoder bank a segment segment segment segment segment segment segment segment must select one channel must select one segment
preliminary data sheet m14412ej3v0ds00 12 m m m m pd45125421, 45125821, 45125161 data size of segment and channel memory cell 8 k (8192) bits 1 row 2 k (2048) bits 4 segments 16 channels 2 k (2048) bits 2 1 3 45 16 input and output buffer 0 1 2 3 x 4 bits organization 512 bits 2048 (2k) bits / 4 column selector one channel density 2048 (2k) bits input and output buffer 0 1 2 3 4 5 7 6 x 8 bits organization column selector 256 bits 2048 (2k) bits / 8 one channel density 2048 (2k) bits input and output buffer 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x 16 bits organization column selector 128 bits 2048 (2k) bits / 16 one channel density 2048 (2k) bits one segment means one data transfer size at the prefetch and restore operation.
preliminary data sheet m14412ej3v0ds00 13 m m m m pd45125421, 45125821, 45125161 1. input / output pin function (1/3) pin name input/output function clk input clk is the master clock input. other inputs signals for all commands are referenced to the clk rising edge. cke input cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise it is invalid. if the clk rising edge is invalid, the internal clock is not issued and the virtualchannel sdram suspends operation. when the virtualchannel sdram is not in burst mode and cke is negated, the device enters power down mode. during power down mode, cke must remain low. /cs input chip select. /cs low starts the command input cycle, which occurs on rising edge of clk. during /cs high, commands are ignored but operations continue. /ras, /cas, /we input command inputs. the combination of these signals defines the command being entered. for details, refer to the command table in command functions. the symbol names (/ras, /cas, /we) do not refer to the functional meanings used for conventional dram. dqm for x8,x4 devices udqm ldqm for x16 device input for x4, x8 devices dqm controls i/o buffers. for x16 device udqm and ldqm control upper byte and lower byte i/o buffers, respectively. in read mode dqm controls the output buffers like a conventional /oe pin. dqm high and dqm low turn the output buffers off and on, respectively. the dqm latency for the read is two clo cks. in write mode dqm controls the word mask. input data is written to the memory cell if dqm is low but not if dqm is high. the dqm latency for the write is zero. dq0 - dq3 dq0 - dq7 dq0 - dq15 input / output dq pins have the same function as i/o pins on a standard synchronous dram. dq0 - dq3 (for x 4 device) dq0 - dq7 (for x 8 device) dq0 - dq15 (for x 16 device) nc - no connect. leave these pins unconnected. v cc v ss (power supply) v cc and v ss are power supply pins for internal circuits. v cc q v ss q (power supply) v cc q and v ss q are power supply pins for the output buffers.
preliminary data sheet m14412ej3v0ds00 14 m m m m pd45125421, 45125821, 45125161 (2/3) pin name input / output function a0 - a13 input address specification. these pins provide memory source and target addresses (bank, row, column, etc.), and channel addresses. row address row address is determined by a0 - a12 at the clk (clock) rising edge in the active command cycle. it does not depend on the bit organization. column address column address is determined by a0 - a7 and a10 at the clk rising edge in the read or write command cycle. it depends on the bit organization. : a0 - a7, a10 for x4 device : a0 - a7 for x8 device : a0 - a6 for x16 device. bank address(a13) a13 is the bank select signal. in command cycle, a13 low select bank a, and a13 high select bank b.
preliminary data sheet m14412ej3v0ds00 15 m m m m pd45125421, 45125821, 45125161 (3/3) pin name input / output function a0 - a13 input channel address(a8, a9, a10, a11, a12) a8, a9, a11, a12 are the channel select signals. in prefetch, restore, read and write operations, channel is determined by a8, a9, a11 and a12. channel number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 a12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 in set register operation, channel is determined by a9, a10, a11 and a12. channel number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a9 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 a12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 segment address(a0, a1, a10, a13) a0, a1, a10, a13 are the segment select signals. in prefetch and restore operations, column address in channel is determined by a0, a1. in prefetch read operation, segment is determined by a10, a13. auto precharge address(a10) a10 defines the precharge mode. in the precharge command cycle high level: all banks are precharged. low level: only the bank selected by a13 is precharged. in the prefetch or restore command cycle high level: auto precharge low level: without auto precharge
preliminary data sheet m14412ej3v0ds00 16 m m m m pd45125421, 45125821, 45125161 2. truth table 2.1 command execution all commands are executed with the signal combination at the rising edge of the clock (clk), /cs (chip select) must be low at the command input cycle. cke (clock enable) must be high at one clock before the command input cycle as shown in below. the state of the /ras, /cas, and /we signals specifies the command function to be executed. some commands have the same signal combination for /ras, /cas, and /we and are distinguished by some of address input signals. when /cs becomes high, operations continue as specified in the command, but further commands (signal states that would specify a command) are not registered until /cs becomes low. this state is device deselect. /ras /cas /we address cke clk h n - 1 n n + 1 command l /cs
preliminary data sheet m14412ej3v0ds00 17 m m m m pd45125421, 45125821, 45125161 2.2 command truth table function symbol /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 device deselect desl h x x x x x x x x x x x x x x x x x no operation nop l h h h x x x x x x x x x x x x x x prefetch without auto precharge pfc l h h l ba cha. cha. l cha. cha. l l l x x x seg. seg. prefetch with auto precharge pfca l h h l ba cha. cha. h cha. cha. l l l x x x seg. seg. restore without auto precharge rst l h h l ba cha. cha. l cha. cha. h x x x x x seg. seg. restore with auto precharge rsta l h h l ba cha. cha. h cha. cha. h x x x x x seg. seg. channel read read l h l h x cha. cha. col. cha. cha. col. col. col. col. col. col. col. col. channel write writ l h l l l cha. cha. col. cha. cha. col. col. col. col. col. col. col. col. bank activate act l l h h ba row row row row row row row row row row row row row prefetch read with auto precharge pfr n ote l l h l seg. cha. cha. seg. cha. cha. col. col. col. col. col. col. col. col. precharge selected bank pre l l l l ba x x l x x x x l x x x x x precharge all banks pall l l l l x x x h x x x x l x x x x x set register operation sclr l l l l l l l l l l l l h prl rl rl rl wt sccr l l l l l cha. cha. cha. cha. l l h h x x bl bl bl note for x4 bits organization, this command is illegal. remark abbreviations in the table mean as follows. h : high level l : low level x : high or low level (don' t care) row : row address col. : column address ba : bank address cha. : channel address seg. : segment address bl : burst length rl : read latency prl : prefetch read latency wt : wrap type
preliminary data sheet m14412ej3v0ds00 18 m m m m pd45125421, 45125821, 45125161 2.3 cke truth table current state function symbol cke /cs /ras /cas /we address nC1 n activating clock suspend mode entry C h l x x x x x any clock suspend C l l x x x x x clock suspend clock suspend mode exit C l h x x x x x idle auto refresh command ref h h l l l h x idle self refresh entry self h l l l l h x self refresh self refresh exit C l h l h h h x l h h x x x x idle power down entry C h l x x x x x power down power down exit C l h h x x x x l h h h x remark h: high level, l: low level, x: high or low level (don' t care)
preliminary data sheet m14412ej3v0ds00 19 m m m m pd45125421, 45125821, 45125161 3. commands device deselect (desl) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 highxxxxxxxxxxxxxxxxx remark x: high or low level (don' t care) the device is deselected state by this command. clk cke h /ras /we /cas a0 to a13 /cs
preliminary data sheet m14412ej3v0ds00 20 m m m m pd45125421, 45125821, 45125161 no operation (nop) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 lowhighhighhighxxxxxxxxxxxxxx remark x: high or low level (don' t care) this command is not a execution command. no operations begin or terminate by this command. /cs clk cke h /ras /we /cas a0 to a13
preliminary data sheet m14412ej3v0ds00 21 m m m m pd45125421, 45125821, 45125161 prefetch without auto precharge (pfc) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high high low ba cha. cha. low cha. cha. low low low x x x seg. seg. remark ba: bank address, cha.: channel address, x: high or low level (don' t care), seg.: segment address this command needs to follow bank activate (act) command. this command fetches data from a segment of the activated row in a bank to a channel buffer which is chosen by channel address. the segment and bank fields specify the source segment and bank. in addition, the channel address field specifies the destination channel. a10 specify the optional precharge operation. in case of a10: low, without auto precharge operation occurs. in case of a10: high, with auto precharge operation occurs after data fetch operation. (please refer to pfca command.) (bank precharge is necessary after data fetch.) this fetched command can be issued continuously without any precharge operation. for instance, when the first operation has been done from one of segment on activated row area to one of channel, if the second prefetch operation is required from same activated row, but different channel, the second prefetch command can be issued without any precharge operation. t ppd (pfc to pfc/pfca command period) is required between first and second prefetch command. when the new row address area need to be activated on same bank, bank precharge is necessary after this pfc command. t ppl (pfc to pre command period) is required between pfc and pre. fetched data into the channel buffer remains available for channel read and channel write operations. /cs clk cke h /ras /we /cas a13 valid a12 valid a1 valid a2 to a4 bank select channel address a11 valid a10 a9 valid channel address a8 valid a7 segment address a0 valid a6 a5
preliminary data sheet m14412ej3v0ds00 22 m m m m pd45125421, 45125821, 45125161 prefetch with auto precharge (pfca) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high high low ba cha. cha. high cha. cha. low low low x x x seg. seg. remark ba: bank address, cha.: channel address, x: high or low level (don' t care), seg.: segment address this command needs to follow bank activate (act) command. this command fetches data from a segment of the activated row in a bank to a channel buffer, and precharge operation is performed automatically, which closes the activated row after data fetch operation. the segment and bank fields specify the source segment and bank. in addition, the channel address field specifies the destination channel. a10 specify the optional precharge operation. in case of a10: low, without auto precharge operation occurs. (please refer to pfc command.) in case of a10: high, with auto precharge operation occurs after data fetch operation. fetched data into the channel buffer remains available for channel read and channel write operations. /cs clk cke h /we /cas a13 valid a12 valid a1 valid /ras a2 to a4 bank select channel address a11 valid a9 valid channel address a8 valid a7 segment address a0 valid a6 a5 a10
preliminary data sheet m14412ej3v0ds00 23 m m m m pd45125421, 45125821, 45125161 restore without auto precharge (rst) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high high low ba cha. cha. low cha. cha. high x x x x x seg. seg. remark ba: bank address, cha.: channel address, x: high or low level (don' t care), seg.: segment address this command transfers data from a channel buffer to a segment of a row which is going to be activated by following act command. the command bank address field specifies the destination bank. the channel address fields specify the source channel. the segment number field specifies the destination segment. a10 specify the optional precharge operation. in case of a10: low, without auto precharge operation occurs. (please refer to rsta command.) in case of a10: high, with auto precharge operation occurs after data fetch operation. /cs clk cke h /ras /we /cas a13 valid a12 valid a1 valid a2 to a6 bank select channel address a11 valid a10 a9 valid channel address a8 valid a7 segment address a0 valid
preliminary data sheet m14412ej3v0ds00 24 m m m m pd45125421, 45125821, 45125161 restore with auto precharge (rsta) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high high low ba cha. cha. high cha. cha. high x x x x x seg. seg. remark ba: bank address, cha.: channel address, x: high or low level (don' t care), seg.: segment address this command transfers data from a channel buffer to a segment of a row which is going to be activated by following act command. in addition, precharge operation is performed automatically which closes the active row after data restore operation. the command bank address field specifies the destination bank. the channel address fields specify the source channel. the segment number field specifies the destination segment. a10 specify the optional precharge operation. in case of a10: low, without auto precharge operation occurs. (please refer to rsta command.) in case of a10: high, with auto precharge operation occurs after data fetch operation. /cs clk cke h /ras /we /cas a13 valid a12 valid a1 valid a2 to a6 bank select channel address a11 valid a10 a9 valid channel address a8 valid a7 segment address a0 valid
preliminary data sheet m14412ej3v0ds00 25 m m m m pd45125421, 45125821, 45125161 channel read (read) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high low high x cha. cha. col. cha. cha. col. col. col. col. col. col. col. col. remark x: high or low level (don' t care), cha.: channel address, col.: column address channel read (read) reads data words from a channel buffer onto the data bus (dq). the channel address field specifies the source channel. the column address field specifies the starting location of the data word in the buffer (data words may be 4, 8, or 16 bits.). the burst-length field in the channel control register for the channel specifies the number of data words to complete the read operation. /cs clk cke h /ras /we /cas a13 a0 to a7 valid a12 valid channel address a11 valid a9 valid channel address a8 valid column address a10 valid column address
preliminary data sheet m14412ej3v0ds00 26 m m m m pd45125421, 45125821, 45125161 channel write (writ) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high low low low cha. cha. col. cha. cha. col. col. col. col. col. col. col. col. remark x: high or low level (don' t care), cha.: channel address, col.: column address channel write(writ) writes data from the data bus (dq) into a channel buffer. the channel address field specifies the destination channel. the column address field specifies the starting location of the data word in the buffer (data words may be 4, 8 or 16 bits.). the burst-length field in the channel control register for the channel specifies the number of data words to complete the write operation. /cs clk cke h /ras /we /cas a0 to a7 valid a12 valid channel address a11 valid a9 valid channel address a8 valid column address a10 valid column address a13
preliminary data sheet m14412ej3v0ds00 27 m m m m pd45125421, 45125821, 45125161 bank activate (act) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low high high ba row row row row row row row row row row row row row remark ba: bank address, row: row address activation causes row contents to be placed into the bank's sense amplifier. the command bank address and row address fields specify bank and row. this device has two banks, each with 8,192 rows. this command activates the bank selected by bank address(a13) and a row address selected by a0 through a12. the row remains active for access until a precharge command is issued to the bank. a precharge command must be issued before another row can be activated in that bank. each bank can have one row active. this command corresponds to a conventional drams /ras falling. /cs clk cke h /ras /we /cas a13 a0 to a12 valid valid bank select row address
preliminary data sheet m14412ej3v0ds00 28 m m m m pd45125421, 45125821, 45125161 prefetch read with auto precharge (pfr) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low high low seg. cha. cha. seg. cha. cha. col. col. col. col. col. col. col. col. remark seg.: segment address, cha.: channel address, col.: column address this command needs to follow bank activate (act) command. this command fetches data from a segment of the activated row in a bank to a channel buffer, and reads data words from a channel buffer onto the data bus (dq). in addition, precharge operation is performed automatically, which closes the activated row after data fetch operation. the segment fields specify the source segment. in addition, the channel address field specifies the destination channel. the column address field specifies the starting location of the data word in the buffer (data words may be 4, 8, or 16 bits.). the burst-length field in the channel control register for the channel specifies the number of data words to complete the read operation. for x4 bits organization, this command is illegal. /cs clk cke h /we a0 to a7 valid a12 valid channel address a11 valid a9 valid channel address a8 valid column address /ras /cas segment address a13 valid segment address a10 valid
preliminary data sheet m14412ej3v0ds00 29 m m m m pd45125421, 45125821, 45125161 precharge selected bank (pre) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low low low ba x x low x x x x low x x x x x remark ba: bank address, x: high or low level (don' t care) this command closes (deactivates) an activated row in a bank, in order to prepare the bank for an activate or restore command to activate a new row. after precharging, a bank is in the idle state. the bank field specifies the bank to precharge and a10 low specifies the command. after this command, t rp (precharge to activate command period) must be satisfied for next activate command to precharging bank. this command corresponds to a conventional drams /ras rising. /cs clk cke h /we /ras a6 to a9 a11,a12 a10 a13 valid bank select /cas a0 to a4 a5
preliminary data sheet m14412ej3v0ds00 30 m m m m pd45125421, 45125821, 45125161 precharge all banks (pall) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low low low x x x high x x x x low x x x x x remark x: high or low level (don' t care) the signal combination is reserved (with command modifier a10 high). the pall command is typically used during auto refresh operation and initialization. replace with precharge commands for each bank. /cs clk cke h /we /ras a6 to a9 a11 to a13 /cas a0 to a4 a5 a10
preliminary data sheet m14412ej3v0ds00 31 m m m m pd45125421, 45125821, 45125161 set channel latency register (sclr) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low low low low low low low low low low low high prl rl rl rl wt remark prl: prefetch read latency, rl: read latency, wt: wrap type this command sets the read latency value which specifies read delay time in channel read operation. in addition, this command sets the wrap type which specifies the order(sequential or interleave) in which the burst data will be addressed. moreover, this command sets the read latency value which specifies read delay time in prefetch read operation. the commands can only be executed with all memory banks idle and no burst operations in progress. /cs clk cke h /ras /we /cas a3 a6 to a13 read latency a2 a1 a0 valid wrap type valid valid valid a5 prefetch read latency a4 valid
preliminary data sheet m14412ej3v0ds00 32 m m m m pd45125421, 45125821, 45125161 set channel control register (sccr) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low low low low cha. cha. cha. cha. low low high high x x bl bl bl remark cha.: channel address, bl: burst length, x: high or low level (don' t care) this command sets burst length in channel address. burst length for the 0-15 channels is the same. this command is executed during initialization. the commands can only be executed with all memory banks idle and no burst operations in progress. /cs clk cke h /ras /we /cas a7,a8 a13 a12 burst length a2 a1 a0 valid valid valid valid a11 valid a10 valid a9 valid channel address a5,a6 a3,a4
preliminary data sheet m14412ej3v0ds00 33 m m m m pd45125421, 45125821, 45125161 auto refresh (ref) cke /cs /ras /cas /we address nC1 n high high low low low high high or low level (don' t care) this command is a request to begin the auto refresh operation. the refresh address is generated internally. before executing auto refresh, all banks must be in the idle state. after this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. during t rc period (from refresh command to refresh or activate command), the virtualchannel sdram cannot accept any other command. clk cke h n - 1n /ras /cas a0 to a13 h /we /cs
preliminary data sheet m14412ej3v0ds00 34 m m m m pd45125421, 45125821, 45125161 self refresh (self) cke /cs /ras /cas /we address nC1 n high low low low low high high or low level (don' t care) after the command execution, self refresh operation continues while cke remains low. during self refresh mode, the internal refresh controller takes care of refresh interval and refresh operation. there is no need for external control. before executing self refresh, both banks must be in the idle state. during self refresh mode, both background and foreground operation can not be executed. /cs clk cke /ras n - 1n /cas a0 to a13 hl /we
preliminary data sheet m14412ej3v0ds00 35 m m m m pd45125421, 45125821, 45125161 4. simplified state diagram active stand by active power down prefetch with auto precharge auto refresh precharge restore with auto precharge self refresh power down set channel latency register channel read channel write automatic sequence manual input background operation foreground operation restore without auto precharge prefetch without auto precharge prefetch read write suspend read suspend idle stand by power on cke:low cke:high cke:low cke:high writ read cke:low cke:high self self exit pre set channel control register sclr sccr ref pfc row active cke:high cke:low read read act read read read read read read pfr pre pre pre pre rst rst rst rsta rsta rsta act act act writ writ writ writ writ writ writ pfc pfca pfca pfca pfca pfc pfc act read writ
preliminary data sheet m14412ej3v0ds00 36 m m m m pd45125421, 45125821, 45125161 5. prefetch read operation ( ( ( ( optional ) ) ) ) this operation fetches data from a segment of the activated row in a bank to a channel buffer, and reads data words from a channel buffer onto the data bus (dq). in addition, precharge operation is performed automatically, which closes the activated row after data fetch operation. for x4 bits organization, prefetch read operation can not be used (pfr command is illegal). row decoder bank b row decoder bank a read operation 16 channels input and output buffer dq dq segment segment segment segment segment segment segment segment prefetch read operation prefetch operation clk command dq act pfc read q2 q1 q0 0 2345678 1 hi-z ( burst length = 4 ) q3 command act pfr dq q1 q0 hi-z q2 q3 read latency = 2 prefetch read latency = 4 t apd t aprd the relationship between clock frequency and read latency, prefetch read latency clock frequency mhz(max.) read latency prefetch read latency 133 100 24 67 50 12
preliminary data sheet m14412ej3v0ds00 37 m m m m pd45125421, 45125821, 45125161 6. write operation and restore operation write command proceeds write operation to the channel. when the system needs to refill the channel with new data, restore operation may be necessary. the restore operation needs both restore command and active command. restore command must be first command. restore operation is also fully associative operation. the data in the channel can be transferred to anywhere on memory core array. another write and read operation to another channel can proceed during this restore operation. the another background operation is illegal while t rad (rst/rsta to act(r) command delay time). in addition, the foreground operation to the same channel set by rst command is illegal too. row decoder bank b row decoder bank a restore operation (from channel to segment) write operation ( to channel ) 16 channels input and output buffer dq dq segment segment segment segment segment segment segment segment clk command channel address a13 a10 dq dqm writ pre row 0 col. 0 banka l d1-1 d1-0 0 2345678 1 t ras t rcd hi-z ( burst length = 2 ) segment channel 1 t rad rst act (r) banka banka channel 1 remark act(r) command is act command after rst command. without auto precharge col. 1 read banka channel 1 with auto precharge q1-1
preliminary data sheet m14412ej3v0ds00 38 m m m m pd45125421, 45125821, 45125161 7. set register operation 1 1 1 1 use in future a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 1 0 jedec standard test set (refresh counter test) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 1 0 0 0 0 0 0 don t care , vender specification a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 valid data input 1 1 don t care , mode register set a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 0 0 a6(0) set channel latency register (sclr) a6(1) set channel control register (sccr) valid data input don t care , valid data input valid data input valid data input
preliminary data sheet m14412ej3v0ds00 39 m m m m pd45125421, 45125821, 45125161 8. set channel latency register (sclr) /cs clk cke h /ras /we /cas a6 a1 a2 a3 a7 valid valid valid a13 a8 a9 a10 a11 a12 a0 valid wrap type sequential interleave a0 0 1 wrap type read latency 1 1 2 2 a1 1 1 0 0 a4 0 1 0 1 a2 0 0 1 1 read latency and prefetch read latency a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 0 0 0 0 0 0 0 0 1 a5 a4 valid remark for x4 bits organization, prefetch read latency (a4) is don't care. prefetch read latency 2 3 3 4 remark legal illegal illegal legal
preliminary data sheet m14412ej3v0ds00 40 m m m m pd45125421, 45125821, 45125161 9. set channel control register (sccr) sequential 1 2 4 8 16 reserved reserved reserved interleave 1 2 4 8 16 reserved reserved reserved burst length a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 1 0 0 channel address burst length don t care , /cs clk cke h /ras /we /cas a12 valid a2 valid a1 valid a0 valid a11 valid a10 valid a9 valid a8 a6 a3 a7 a4 1 a13 a5 channel number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a9 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 channel number a12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 a0 0 1 0 1 0 1 0 1 a1 0 0 1 1 0 0 1 1 a2 0 0 0 0 1 1 1 1 0
preliminary data sheet m14412ej3v0ds00 41 m m m m pd45125421, 45125821, 45125161 10. burst length and sequence [burst of two] starting address addressing sequence addressing sequence (column address a0) sequential interleave (binary) (decimal) (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 [burst of four] starting address addressing sequence addressing sequence (column address a1,a0) sequential interleave (binary) (decimal) (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [burst of eight] starting address addressing sequence addressing sequence (column address a2-a0) sequential interleave (binary) (decimal) (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
preliminary data sheet m14412ej3v0ds00 42 m m m m pd45125421, 45125821, 45125161 [burst of sixteen] starting address addressing sequence addressing sequence (column address a3-a0) sequential interleave (binary) (decimal) (decimal) 0000 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 0001 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0 1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14 0010 2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1 2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13 0011 3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,2 3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12 0100 4,5,6,7,8,9,10,11,12,13,14,15,0,1,2,3 4,5,6,7,0,1,2,3,12,13,14,15,8,9,10,11 0101 5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4 5,4,7,6,1,0,3,2,13,12,15,14,9,8,11,10 0110 6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5 6,7,4,5,2,3,0,1,14,15,12,13,10,11,8,9 0111 7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8 1000 8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7 8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7 1001 9,10,11,12,13,14,15,0,1,2,3,4,5,6,7,8 9,8,11,10,13,12,15,14,1,0,3,2,5,4,7,6 1010 10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9 10,11,8,9,14,15,12,13,2,3,0,1,6,7,4,5 1011 11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10 11,10,9,8,15,14,13,12,3,2,1,0,7,6,5,4 1100 12,13,14,15,0,1,2,3,4,5,6,7,8,9,10,11 12,13,14,15,8,9,10,11,4,5,6,7,0,1,2,3 1101 13,14,15,0,1,2,3,4,5,6,7,8,9,10,11,12 13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2 1110 14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13 14,15,12,13,10,11,8,9,6,7,4,5,2,3,0,1 1111 15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0
preliminary data sheet m14412ej3v0ds00 43 m m m m pd45125421, 45125821, 45125161 11. initialization the virtualchannel sdram is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, when power is applied, a 100 m s or longer pause must precede any signal toggling. (2) after the pause, both banks must be precharged using the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum t rp is satisfied, the mode register can be programmed. after the mode register set cycle, t rsc (2 clk minimum) pause must be satisfied as well. (4) two or more auto refresh must be performed. remarks 1. the sequence of mode register programming and refresh above may be transposed. 2. cke and dqm must be held high until the precharge command is issued to ensure data-bus hi-z.
preliminary data sheet m14412ej3v0ds00 44 m m m m pd45125421, 45125821, 45125161 12. electrical specifications (target) all voltages are referenced to v ss (gnd). after power up, wait more than 100 m s and then, execute power on sequence and auto refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc , v cc q C0.5 to +4.6 v voltage on input pin relative to gnd v t C0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 1w operating ambient temperature t a 0 to 70 c storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc , v cc q 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 note1 v low level input voltage v il C0.3 note2 +0.8 v operating ambient temperature t a 070 c notes 1. v ih (max.) = v cc + 1.5 v (pulse width 5 ns) 2. v il (min.) = C1.5 v (pulse width 5 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 clk -a75 2.5 3.5 pf -a10 2.5 4.0 c i2 a0 - a13,cke, /cs,/ras, /cas, -a75 2.5 3.8 /we,dqm, udqm, ldqm -a10 2.5 4.0 data input/output capacitance c i/o dq 4.0 6.5 pf h
preliminary data sheet m14412ej3v0ds00 45 m m m m pd45125421, 45125821, 45125161 dc characteristics 1 (recommended operating conditions unless otherwise noted) parameter symbol test condition grade read maximum. unit notes latency x4 x8 x16 operating current i cc1 pt rc 3 t rc(min.) -a75 rl=1 tbd ma 1 ( prefetch mode at one prefetch is executed one time rl=2 150 bank active ) during t rc . -a10 rl=1 tbd rl=2 130 operating current i cc1 rt rc 3 t rc(min.) -a75 rl=1 tbd ma 1 ( restore mode at one rl=2 150 bank active ) -a10 rl=1 tbd rl=2 130 precharge standby current i cc2 p cke v il(max.) , t ck = 15 ns 1.2 ma in power down mode i cc2 ps cke v il(max.) , t ck = 1.2 precharge standby current in non power down mode i cc2 n cke 3 v ih(min.) , t ck = 15 ns /cs 3 v ih(min.) , input signals are changed one time during 30 ns. 20 ma i cc2 ns cke 3 v ih(min.) , t ck = input signals are stable. 10 active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 6 ma power down mode i cc3 ps cke v il(max.) , t ck = 6 active standby current in non power down mode i cc3 n cke 3 v ih(min.) , t ck = 15 ns /cs 3 v ih(min.) input signals are changed one time during 30 ns. 30 ma i cc3 ns cke 3 v ih(min.) ,t ck = input signals are stable. 20 operating current i cc4 t ck 3 t ck(min.) , -a75 rl=1 tbd ma 2 (burst mode) i o = 0 ma, rl=2 60 65 75 background: precharge standby -a10 rl=1 tbd rl=2 45 50 75 auto refresh current i cc5 t rcf 3 t rcf(min.) -a75 rl=1 tbd ma 3 rl=2 230 -a10 rl=1 tbd rl=2 220 self refresh current i cc6 cke 0.2 v2ma notes 1. i cc1 depends on cycle rates. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck(min.) . 2 .i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck(min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck(min.) . dc characteristics 2 (recommended operating conditions unless otherwise noted) parameter symbol test condition min. typ. max. unit note input leakage current i i(l) 0 v i v cc q, v cc q = v cc all other pins not under test = 0 v C 1.0 C + 1.0 m a output leakage current i o(l) 0 v o v cc q, d out is disabled. C 1.5 C + 1.5 m a high level output voltage v oh i o = C 4 ma 2.4 CC v low level output voltage v ol i o = + 4 ma CC0.4 v h
preliminary data sheet m14412ej3v0ds00 46 m m m m pd45125421, 45125821, 45125161 ac characteristics (recommended operating conditions unless otherwise noted) test conditions ac measurements assume t t = 1 ns. reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih(min.) and v il(max.) . an access time is measured at 1.4 v. t ck2 t s t h t ds valid valid valid valid valid t ac2 hi-z hi-z t ac2 t lz t oh2 t hz t dh t ds t dh t ch t ch t cl clk (input) command address dqm data (input) data (output) cke t cks t ckh t ck2 t cl
preliminary data sheet m14412ej3v0ds00 47 m m m m pd45125421, 45125821, 45125161 ac characteristics(target) parameter symbol -a75 -a10 unit note min. max. min. max. clock cycle time rl=1 t ck1 15 - 20 - ns rl=2 t ck2 7.5 - 10 - ns access time from clk rl=1 t ac1 - 12 - 15 ns 1 rl=2 t ac2 - 5.4 - 6ns clk high level width t ch 2.5 - 3 - ns clk low level width t cl 2.5 - 3 - ns data-out hold time t oh 2.7 - 3 - ns 1 data-out low-impedance time t lz 0 - 0 - ns data-out high-impedance time rl=1 t hz1 2.512315ns rl=2 t hz2 2.5 5.4 3 6 ns data-in setup time t ds 1.5 - 2 - ns data-in hold time t dh 0.8 - 1 - ns address, command, dqm setup time t s 1.5 - 2 - ns address, command, dqm hold time t h 0.8 - 1 - ns cke setup time t cks 1.5 - 2 - ns cke hold time t ckh 0.8 - 1 - ns cke setup time (power down exit) t cksp 1.5 - 2 - ns transition time t t 0.830130ns refresh time (4,096 refresh cycle) t ref - 64 - 64 ms mode register set cycle time t rsc 2 - 2 - clk note1 output load. output z = 50 w 50 pf h h h
preliminary data sheet m14412ej3v0ds00 48 m m m m pd45125421, 45125821, 45125161 ac characteristics (background to background operation) parameter symbol -a 75 -a10 unit notes min. max. min. max. same bank operation act to act/ref command period t rc 67.5 - 80 - ns ref to ref/ act command period t rcf 67.5 - 90 - ns act to pre command period t ras 52.5 120,000 60 120,000 ns pre to act / ref command period t rp 20 - 20 - ns act to pfc/pfca command delay time t apd 15 - 20 - ns act to pfr command delay time (prefetch read operation) t aprd 15 - 20 - ns 3 pfc to pre command delay time t ppl 22.5 - 30 - ns pfca / pfr to act/ref command delay time t pal 45 - 50 - ns rst / rsta to act(r) note1 command delay time t rad 7.5 30 10 40 ns 2 same,other bank operation act(r) note1 to pfc/pfca/pfr command delay time t rpd 37.5 - 40 - ns pfc to pfc / pfca command delay time t ppd 22.5 - 30 - ns other bank operation act to act/act(r) or act(r) to act command delay time t rrd 15 - 20 - ns act(r) to act(r) command delay time t rrdr 30 - 40 - ns pfc /pfca to rst /rsta command delay time t prd 22.5 - 30 - ns notes 1 act(r) command is act command after rst command. 2 the another background operation and same channel foreground operation are illegal while t rad period. 3 for x4 bits organization, prefetch read operation can not used.
preliminary data sheet m14412ej3v0ds00 49 m m m m pd45125421, 45125821, 45125161 ac characteristics (foreground to foreground operation) parameter symbol -a75 -a 10 unit note min. max. min. max. read/write to read/write command delay time t ccd 7.5 - 10 - ns ac characteristics (background to foreground operation) (after same channel prefetch/restore) parameter symbol -a75 -a 10 unit note min. max. min. max. pfc/pfca to read/write command delay time t pcd 15 - 20 - ns act(r) to read/write command delay time t rcd 30 - 40 - ns 1 note1 act(r) command is act command after rst command.
preliminary data sheet m14412ej3v0ds00 50 m m m m pd45125421, 45125821, 45125161 power on sequence and auto refresh clk 4678 5 17 25 26 16 command address a10 a7, a8 t rp pall h sclr sccr ref row 1 act banka t rsc a6 ref a5 l read latency wrap type l l burst length channel l h t rsc t rcf t rcf dq dqm hi-z 0123 t rsc sccr burst length channel l h 1st sccr 2nd sccr it is necessary to input sccr command 16 times (16 channels) to set burst length for channel.
preliminary data sheet m14412ej3v0ds00 51 m m m m pd45125421, 45125821, 45125161 /cs function (only /cs signal needs to be issued at minimum rate) clk ( read latency = 2, burst length = 2 ) 0 2345678 1 9 111213141516 10 command act pfc read writ cke /ras /cas /we /cs dq dqm l hi-z q1-0 q1-1 d1-0 d1-1 a8,a9,a11,a12 row channel channel channel a13 bank bank a10 row a5,a6,a7 row column column a2,a3,a4 row column column a0,a1 row segment column column h
preliminary data sheet m14412ej3v0ds00 52 m m m m pd45125421, 45125821, 45125161 clock suspension during burst read (using cke function) clk command channel address a13 a10 dq dqm ( read latency = 2, burst length = 4 ) 0 2345678 1 t apd l row 0 act banka 9 111213141516 10 segment 1 pfc banka channel 1 col. 0 read channel 1 hi-z q1-3 t pcd cke q1-0 q1-1 q1-2 auto precharge without 1 clock suspend 2 clocks suspend 3 clocks suspend
preliminary data sheet m14412ej3v0ds00 53 m m m m pd45125421, 45125821, 45125161 clock suspension during burst write (using cke function) clk command channel address a13 a10 dq dqm ( burst length = 4 ) 0 2345678 1 t apd l row 0 act banka 9 111213141516 10 segment 1 pfc banka channel 1 col. 0 writ channel 1 hi-z t pcd cke d1-0 auto precharge without 1 clock suspend 2 clocks suspend 3 clocks suspend d1-1 d1-2 d1-3
preliminary data sheet m14412ej3v0ds00 54 m m m m pd45125421, 45125821, 45125161 power down mode clk command channel address a13 a10 dq dqm ( read latency = 2, burst length = 2 ) 0 2345678 1 l row 0 act banka 9 111213141516 10 segment 1 pfc banka channel 1 col. 0 read channel 1 hi-z cke q1-0 q1-1 auto precharge without power down mode entry power down mode exit power down mode entry power down mode exit t cksp t cksp pre banka l active standby precharge standby
preliminary data sheet m14412ej3v0ds00 55 m m m m pd45125421, 45125821, 45125161 set register operation clk command channel address a6 a7 to a8 dq dqm sclr l l l l sclr 0 2345678 1 t rsc t rsc hi-z l channel, burst lenght h l sccr read latency, wrap type read latency, wrap type
preliminary data sheet m14412ej3v0ds00 56 m m m m pd45125421, 45125821, 45125161 read operation read 0234 1 clk command dq dqm q0 q1 q2 hi-z l q3 ( burst length = 4 ) read latency = 2 write operation writ 023 1 clk command dq dqm d1 d2 d3 l ( burst length = 4 ) write latency = 0 d0
preliminary data sheet m14412ej3v0ds00 57 m m m m pd45125421, 45125821, 45125161 dqm operation in read clk dq dqm q0 q1 q3 hi-z hi-z read mask latency = 2 mask ( burst length = 4 ) dqm operation in write clk dq dqm mask mask ( burst length = 4 ) d1 d3 write mask latency = 0
preliminary data sheet m14412ej3v0ds00 58 m m m m pd45125421, 45125821, 45125161 read to read operation clk command channel address dq dqm read col. 0 col. 0 read 0 2345678 1 t ccd hi-z l q1-0 q1-1 q1-2 q1-3 q3-0 q3-1 q3-2 channel 1 channel 3 ( read latency = 2, burst length = 4 ) q3-3 write to write operation clk command channel address dq dqm writ col. 0 col. 0 writ 0 2345678 1 t ccd hi-z l d1-0 d1-1 d1-2 d1-3 d3-0 d3-1 d3-2 d3-3 ( burst length = 4 ) channel 1 channel 3 h
preliminary data sheet m14412ej3v0ds00 59 m m m m pd45125421, 45125821, 45125161 read to write operation clk command channel address dq dqm read col. 0 col. 0 writ 0 2345678 1 t ccd hi-z l q1-0 q1-1 q1-2 d3-0 d3-1 d3-2 ( burst length = 8 ) channel 1 channel 3 d3-3 write to read operation clk command channel address dq dqm writ col. 0 col. 0 read 0 2345678 1 t ccd hi-z hi-z l d1-0 d1-1 d1-2 q3-0 q3-1 q3-2 ( burst length = 8 ) channel 1 channel 3 q3-3
preliminary data sheet m14412ej3v0ds00 60 m m m m pd45125421, 45125821, 45125161 prefetch to read operation without auto precharge (same channel read) clk command channel address a13 a10 dq dqm act pfc read pre act row 0 banka row 1 banka col. 0 banka banka l q1-2 q1-1 q1-0 0 2345678 1 t apd t ras t rc t rp t pcd hi-z l ( read latency = 2, burst length = 4 ) channel 1 channel 1 segment without auto precharge q1-3 prefetch to read operation without auto precharge (other channel read) clk command channel address a13 a10 dq dqm act pfc read read pre row 0 banka col. 7 col. 0 banka banka l q4-2 q5-7 q4-1 q4-0 0 2345678 1 t ppl hi-z l ( read latency = 2, burst length = 4 ) channel 1 segment channel 4 channel 5 without auto precharge
preliminary data sheet m14412ej3v0ds00 61 m m m m pd45125421, 45125821, 45125161 prefetch to write operation without auto precharge (same channel write) clk command channel address a13 a10 dq dqm act act pfc writ pre row 0 banka row 1 col. 0 banka banka banka l d1-2 d1-3 d1-1 d1-0 0 2345678 1 t apd t ras t rc t pcd t rp hi-z l ( burst length = 4 ) channel 1 segment channel 1 without auto precharge prefetch to write operation without auto precharge (other channel write) clk command channel address a13 a10 dq dqm pfc act writ pre writ row 0 banka col. 7 col. 0 banka banka l d4-2 d3-7 d3-8 d4-1 d4-0 0 2345678 1 t ppl hi-z l ( burst length = 4 ) channel 1 segment channel 4 channel 3 d3-9 without auto precharge
preliminary data sheet m14412ej3v0ds00 62 m m m m pd45125421, 45125821, 45125161 read to prefetch to read operation without auto precharge (same channel prefetch) clk command channel address a13 a10 dq dqm pfc read act read pre row 0 banka col. 7 col. 0 banka banka l q1-2 q1-1 q1-0 q1-7 q1-3 0 2345678 1 t apd t pcd t ppl hi-z prefetch termination ( read latency = 2, burst length = 8 ) channel 1 segment channel 1 channel 1 without auto precharge q1-8 read to prefetch to write operation without auto precharge (same channel prefetch) clk command channel address a13 a10 dq dqm pfc read act writ pre row 0 banka col. 3 col. 0 banka banka l q1-2 d1-3 q1-1 q1-0 d1-5 d1-4 0 2345678 1 t apd t pcd t ppl hi-z prefetch termination channel 1 segment channel 1 channel 1 ( read latency = 2, burst length = 8 ) without auto precharge d1-6
preliminary data sheet m14412ej3v0ds00 63 m m m m pd45125421, 45125821, 45125161 write to prefetch to write operation without auto precharge (same channel prefetch) clk command channel address a13 a10 dq dqm act writ writ pre row 0 banka col. 1 col. 0 banka banka l d1-2 d1-1 d1-1 d1-0 d1-2 d1-3 d1-4 0 2345678 1 t apd t ppl t pcd hi-z prefetch termination mask pfc ( burst length = 8 ) segment channel 1 channel 1 channel 1 d1-3 without auto precharge write to prefetch to read operation without auto precharge (same channel prefetch) clk command channel address a13 a10 dq dqm act writ read pre row 0 banka col. 1 col. 0 banka banka l d1-2 d1-1 d1-0 q1-1 d1-3 d1-4 0 2345678 1 t apd t ppl t pcd hi-z prefetch termination mask pfc ( read latency = 2, burst length = 8 ) segment channel 1 channel 1 channel 1 without auto precharge
preliminary data sheet m14412ej3v0ds00 64 m m m m pd45125421, 45125821, 45125161 restore to read operation without auto precharge (same channel read) clk command channel address a13 a10 dq dqm read pre row 0 col. 0 banka l q1-1 q1-0 0 2345678 1 t rcd t ras hi-z l ( read latency = 2, burst length = 4 ) segment channel 1 channel 1 t rad rst act (r) banka banka remark act(r) command is act command after rst command. without auto precharge q1-2 restore to read operation without auto precharge (other channel read) clk command channel address a13 a10 dq dqm read pre row 0 col. 0 banka l q7-3 q7-2 q7-1 q7-0 0 2345678 1 t ras hi-z l ( read latency = 2, burst length = 4 ) segment channel 7 channel 1 t rad rst act (r) banka banka remark act(r) command is act command after rst command. without auto precharge
preliminary data sheet m14412ej3v0ds00 65 m m m m pd45125421, 45125821, 45125161 restore to write operation without auto precharge (same channel write) clk command channel address a13 a10 dq dqm writ pre row 0 col. 0 banka l d1-3 d1-2 d1-1 d1-0 0 2345678 1 t ras t rcd hi-z l ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 1 remark act(r) command is act command after rst command. without auto precharge restore to write operation without auto precharge (other channel write) clk command channel address a13 a10 dq dqm writ pre row 0 col. 0 banka l d3-3 d3-2 d3-1 d3-0 0 2345678 1 t ras hi-z l ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 3 remark act(r) command is act command after rst command. without auto precharge
preliminary data sheet m14412ej3v0ds00 66 m m m m pd45125421, 45125821, 45125161 read to restore to read operation without auto precharge (same channel restore) clk command channel address a13 a10 dq dqm read read pre row 0 col. 4 col. 0 banka l q1-4 q1-1 q1-0 0 2345678 1 t ras t rcd hi-z l restore termination ( read latency = 2, burst length = 4 ) segment channel 1 rst act (r) banka banka channel 1 channel 1 remark act(r) command is act command after rst command. without auto precharge t rad read to restore to write operation without auto precharge (same channel restore) clk command channel address a13 a10 dq dqm read writ pre row 0 col. 5 col. 0 banka l q1-1 q1-0 d1-6 d1-5 0 2345678 1 t ras t rcd hi-z restore termination ( read latency = 2, burst length = 8 ) segment channel 1 rst act (r) banka banka channel 1 channel 1 d1-7 remark act(r) command is act command after rst command. without auto precharge t rad
preliminary data sheet m14412ej3v0ds00 67 m m m m pd45125421, 45125821, 45125161 write to restore to write operation without auto precharge (same channel restore) clk command channel address a13 a10 dq dqm writ writ pre row 0 col. 1 col. 0 banka l d1-1 d1-2 d1-0 d1-2 d1-1 0 2345678 1 t ras t rcd hi-z restore termination mask ( burst length = 8 ) segment channel 1 t rad rst act (r) banka banka channel 1 channel 1 d1-3 remark act(r) command is act command after rst command. without auto precharge write to restore to read operation without auto precharge (same channel restore) clk command channel address a13 a10 dq dqm writ read pre row 0 col. 1 col. 0 banka l d1-1 d1-2 d1-0 q1-1 0 2345678 1 t ras t rcd hi-z restore termination mask ( read latency = 2, burst length = 8 ) segment channel 1 t rad rst act (r) banka banka channel 1 channel 1 remark act(r) command is act command after rst command. without auto precharge
preliminary data sheet m14412ej3v0ds00 68 m m m m pd45125421, 45125821, 45125161 prefetch to prefetch operation without auto precharge clk command channel address a13 a10 dq dqm act act pfc row 0 row 1 banka bankb bankb 0 2345678 1 t rrd t apd t ppd hi-z l segment 1 channel 1 without auto precharge 910 pfc bankb segment 2 channel 8 without auto precharge pfc banka segment 3 channel 2 without auto precharge t ppd prefetch to restore operation without auto precharge (other bank restore) clk command channel address a13 a10 dq dqm act pfc row 0 banka row 0 banka 0 2345678 1 t apd t prd hi-z l segment 1 channel 1 t rad rst act (r) bankb bankb channel 2 segment 1 remark act(r) command is act command after rst command. without auto precharge without auto precharge
preliminary data sheet m14412ej3v0ds00 69 m m m m pd45125421, 45125821, 45125161 prefetch operation with auto precharge clk command channel address a13 a10 dq dqm act act pfc a row 0 banka row 0 banka banka 0 23456789 1 t apd t pal t rc hi-z l auto precharge segment 1 channel 1
preliminary data sheet m14412ej3v0ds00 70 m m m m pd45125421, 45125821, 45125161 restore to prefetch operation without auto precharge restore operation with auto precharge clk command channel address a13 a10 dq dqm pfc pre row 0 bankb row 1 l banka 0 2345678 1 t ras t rrdr t rpd hi-z l segment 1 channel 2 t rad rst act (r) banka banka rst act (r) bankb bankb channel 1 channel 1 segment 3 segment 2 remark act(r) command is act command after rst command. t rad without auto precharge without auto precharge without auto precharge clk command channel address a13 a10 dq dqm row 0 banka 0 23456789 1 t rc hi-z l row 0 row 1 auto precharge segment 1 channel 2 t rad rsta act (r) banka banka t rad bankb bankb segment 3 channel 1 t rrdr act rst act (r) remark act(r) command is act command after rst command. without auto precharge
preliminary data sheet m14412ej3v0ds00 71 m m m m pd45125421, 45125821, 45125161 read to prefetch read with auto precharge operation clk command channel address a13 a10 dq dqm (read latency = 1, prefetch read latency = 2, burst length = 8) 0 2345678 1 t rc t aprd hi-z l row 0 channel 1 act banka 91112 10 q1-8 q1-9 q1-0 q1-1 q1-2 q1-3 q1-4 q1-5 q1-6 q1-7 read col. 8 col. 0 pfr segment channel 1 segment row 1 act banka illegal to input any other background operation. read will be interrupted by pfr. prl=2 (prefetch read latency) 13 t pal write to prefetch read with auto precharge operation clk command channel address a13 a10 dq dqm (read latency = 1, prefetch read latency = 2, burst length = 8) 0 2345678 1 t rc t aprd hi-z l row 0 channel 1 act banka 91112 10 d1-8 d1-9 d1-10 q1-0 q1-1 q1-2 q1-3 q1-4 q1-5 q1-6 q1-7 writ col. 8 col. 0 pfr segment channel 1 segment row 1 act banka writ will be interrupted by pfr. l t pal prl=2 (prefetch read latency) illegal to input any other background operation. h
preliminary data sheet m14412ej3v0ds00 72 m m m m pd45125421, 45125821, 45125161 read to prefetch read with auto precharge operation clk command channel address a13 a10 dq dqm 0 2345678 1 t rc t aprd hi-z l row 0 channel 1 act banka 91112 10 q1-8 q1-9 q1-10 q1-11 q1-0 q1-1 q1-2 q1-3 q1-4 q1-5 read col. 8 col. 0 pfr segment channel 1 segment row 1 act banka illegal to input any other background operation. read will be interrupted by pfr. prl=4 (prefetch read latency) 13 t pal (read latency = 2, prefetch read latency = 4, burst length = 8) write to prefetch read with auto precharge operation clk command channel address a13 a10 dq dqm 0 2345678 1 t rc t aprd hi-z l row 0 channel 1 act banka 91112 10 d1-8 d1-9 d1-10 q1-0 q1-1 q1-2 q1-3 q1-4 writ col. 8 col. 0 pfr segment channel 1 segment row 1 act banka illegal to input any other background operation. writ will be interrupted by pfr. prl=4 (prefetch read latency) l t pal (read latency = 2, prefetch read latency = 4, burst length = 8) d1-11 h h
preliminary data sheet m14412ej3v0ds00 73 m m m m pd45125421, 45125821, 45125161 auto refresh operation clk command address a10 dq dqm h pall ref act 0 2349101112 1 t rp t rcf hi-z l self refresh operation (entry and exit) 109 clk command address a10 dq dqm 0 23456 1 t rp l pall h 96 98 99 100 101 108 97 ref t rcf act cke self refresh entry self refresh exit
preliminary data sheet m14412ej3v0ds00 74 m m m m pd45125421, 45125821, 45125161 13. package drawing notes 1. each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2. dimension "a" does not include mold fiash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. m p a g c n b m d l k j h i e f detail of lead end s 54 28 127 s item b c i l m n 54-pin plastic tsop ( ii ) (10.16 mm (400)) a d e f g h j p millimeters 0.80 (t.p.) 0.91 max. 0.13 0.50 0.10 10.16 0.10 0.10 22.22 0.05 0.10 0.05 0.32 1.1 0.1 11.76 0.20 1.00 + 0.08 - 0.07 0.80 0.20 3 + 7 - 3 k 0.145 + 0.025 - 0.015 s54g5-80-9jf-2 h
preliminary data sheet m14412ej3v0ds00 75 m m m m pd45125421, 45125821, 45125161 14. recommended soldering condition please consult with our sales offices for soldering conditions of the m pd45125 . type of surface mount device m pd45125421g5 : 54-pin plastic tsop (ii) (10.16mm (400)) m pd45125821g5 : 54-pin plastic tsop (ii) (10.16mm (400)) m pd45125161g5 : 54-pin plastic tsop (ii) (10.16mm (400))
preliminary data sheet m14412ej3v0ds00 76 m m m m pd45125421, 45125821, 45125161 15. revision history edition / page description date this edition previous edition type of revision location 1st edition / --- - july 99 2nd edition / p.2 p.2 modification organization july 99 p.2 p.2 modification prefetch read latency for x4 bits organization p.5, 6, 7 p.5, 6, 7 modification organization p.17 p.17 addition note for prefetch read with auto precharge p.28 p.28 modification text regarding x4 bits organization p.36 p.36 modification text regarding x4 bits organization 3rd edition / p.1 p.1 addition features (prefetch read latency for x4 bits organization) nov. 99 p.2 p.2 deletion low power operation p.3 p.3 deletion low power operation p.4 p.4 deletion low power operation p.44 p.44 modification capacitance p.45 p.45 modification dc characteristics 1 p.47 p.47 modification t ck1 , t ck2 , t ac1 , t ac2 , t hz1 , t hz2 p.58 p.58 modification d3-3 p.71 p.71 addition d1-10 p.72 p.72 addition q1-11 (read to prefetch read with auto precharge operation) d1-11 (write to prefetch read with auto precharge operation) p.74 p.74 modification package drawing
preliminary data sheet m14412ej3v0ds00 77 m m m m pd45125421, 45125821, 45125161 [memo]
preliminary data sheet m14412ej3v0ds00 78 m m m m pd45125421, 45125821, 45125161 [memo]
preliminary data sheet m14412ej3v0ds00 79 m m m m pd45125421, 45125821, 45125161 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd45125421, 45125821, 45125161 [memo] virtualchannel and vcmemory are trademarks of nec corporation. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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